The present invention relates to a semiconductor manufacturing technology, and in particular to temperature control for a wafer, which is required for processing a semiconductor wafer in a semiconductor manufacturing apparatus.
These years, the diameter of a wafer to be processed by a semiconductor manufacturing technique, becomes larger and larger so as to fall in a range from 8 to 12 inches. This is because a number of chips, which are available from a single wafer, is to be increased so as to reduce the manufacturing cost. However, as a result, this fact has forced manufacturers of semiconductor equipments into development of an apparatus capable of manufacturing large diameter wafers with enormous investments.
However, on one hand, in view of the relationship to other apparatus in an ordinal manufacturing line, since there is raised such a problem, as an actual circumstance, that all apparatus ordered by clients are not always those which can cope with large diameter wafers, and accordingly, it is required to design, evaluate and produce a new apparatus for every size of wafers desired by a client, resulting in a heavy task to the manufacturer of semiconductor equipments.
Further, due to highly increased integration of semiconductor chips, these years, required machining accuracy has becomes more and more severe, and accordingly, the control of the temperature of a wafer during processing has been more and more important. For example, in order to materialize anisotropic etching in an etching process which requires a high aspect ratio, a process in which etching is made while a side wall is protected by organic polymer is used, but in this process, the degree of formation of the organic polymer serving as a protecting film is changed in dependence upon a temperature.
Accordingly, if the distribution of temperature of a wafer on processing is not uniform, the degree of formation of the protection film on a side wall becomes uneven within the surface of the wafer, and as a result, there is raised a problem of unevenness in an etching shape. Further, in addition to this fact, since the diameter of the wafer becomes larger and larger, as mentioned above, so that the input heat to the wafer tends to be more and more large, that is, for example, a bias power applied to an wafer in a process of etching an inter-layer-dielectric on a manufacturing line for 12 inch diameter wafers becomes higher up to 3 kW, and accordingly, to uniform the temperature distribution in the surface of the wafer causes a very important technical task.
By the way, during plasma processing, a wafer is electrostatically attracted and held to a stage by means of an electrostatic chuck, at this stage, in order to ensure heat transfer between the wafer and the stage, a method in which gas for heat transfer (usually helium is used) is introduced for cooling, has been conventionally used. Further, although the structure of the electrostatic chuck should be changed variously, depending upon a specification of an apparatus, in a typical example, a high thermal conductive metal such as aluminum which is covered on its outer surface with a ceramic film having a thickness of not greater than about 1 mm is used as a base, and a temperature adjusting medium controlled by an external temperature adjusting unit is circulated through the base in order to adjust the temperature.
At this stage, the range of temperature to be controlled is various in dependence upon a process to be used. As to the temperature of the stage for holding the wafer, stable operation is required over a wide range from, for example, xe2x88x9240 deg.C. to a high temperature up to about 100 deg.C. That is, severe requirements have been imposed such that even though heat is inputted to a wafer stage in a plasma processing apparatus in a wide range from a low temperature to a high temperature, a uniform temperature distribution should be materialized over a wafer having a large diameter.
By the way, in an actual electrostatic chuck structure, it is, in general, overhanged from the outer periphery of a wafer by several millimeters, and accordingly, cooling in the vicinity of the outer periphery of the wafer is insufficient, resulting in main cause of deterioration of the temperature distribution over the surface of the wafer. Thus, several ideas for optimizing a method of introduction of helium gas passing between the electrostatic chuck and the back-side surface of the wafer, and the pressure thereof have been conventionally proposed.
However, in a certain method which has been conventionally proposed, since the chuck has a specific structure which is optimized for wafers having a specific size, redesigning has to be additionally made for the electrostatic chuck and the structure of the lower part of the apparatus to which the chuck is mounted, as a whole. Thus, it has been extremely ineffective.
It is noted that a method of improving the temperature distribution over the surface of a wafer is disclosed as a conventional example in JP-A-7-249586 which discloses such a structure that first and second gas passages which are opened at the outer surface of a lower electrode in the vicinity of its outer periphery, and at a plurality of positions therein, and both gas passages in dual systems are connected thereto with first and second gas supply and discharge means, respectively, so as to supply helium gas to the gas passages, independent from each other, in order to cool a semiconductor wafer.
It cannot be safely said that consideration is sufficiently made as to variation of the wafer processing function, and it is raised a problem in view of restraining the cost.
That is, in the conventional technology, since the structure is optimized for a wafer having a certain specific size, it becomes extremely inefficient if the structure is used for wafers having different sizes, and as a result, there is raised such a problem that the cost cannot be restrained from increasing.
Further, since the conventional technology requires the gas supply and discharge means which are independent from each other between the position in the vicinity of the outer periphery of the wafer and the inner periphery thereof, the change of the wafer processing function is complicated and expensive.
Further, in the conventional technology, it is required to set the pressure of helium gas to be fed in the vicinity of the outer periphery of the wafer to a high value, up to about 30 Torr, and accordingly, the attracting force of the electrostatic chuck has to be set to a value which can match with the pressure. As a result, the cost is further increased. It is here estimated that erroneous attraction occurs. The wafer on processing is greatly corrupted, and accordingly, there is raised such a problem that the burden caused by recovery works becomes heavier. Thus, it is inevitable to increase the attraction force.
Detailed explanation will be hereinafter made of the problems inherent to the conventional technology with reference to FIGS. 9 and 10 of which FIG. 9 shows an example of a prior art wafer processing apparatus which are formed for processing a 8 inch wafer and FIG. 10 is an example of a water processing apparatus for processing a 12 inch wafer. At first the prior art shown in FIG. 9 will be explained. In the apparatus shown in FIG. 9, etching gas is introduced into a vacuum chamber 9, as shown, and the pressure in the chamber 9 is set to an appropriate value by adjusting the opening degree of a valve 12 provided upstream of a turbo-molecular pump 13.
Further, a parallel planar type upper electrode 100 is laid in the upper part of the vacuum chamber 9 and is connected to a high frequency power source 8 so as to be applied thereto with a high frequency voltage having a frequency of, for example, 13.56 MHz in order to generate plasma 6 to which a wafer 1 is exposed so as to subject the wafer 1 to an etching process.
Here, in the case of FIG. 9, the diameter of the wafer 1 is 8 inches, and is set on convex part formed on a water stage which has a diameter of 190 mm and which is located being opposed to the upper electrode 10. The reason why the diameter of the convex part on which the wafer is set, is smaller than the diameter of the wafer 1 which is 200 mm (8 inches) is such that the outer surface of the wafer stage 40 is protected from the plasma 6.
In this case, the wafer stage 40 has a diameter of 240 mm, and is formed of a member composed of an aluminum lower cover 42 and a base 41 which are blazed to each other, and is formed on its outer surface with a dielectric film 21 made of ceramic as a main component and having a thickness of 1 mm, by spray coating. The wafer stage 40 is secured to an insulation member 7 fixed to a flange 5, by means of bolts 19, and is electrically insulated from the vacuum chamber 9. In this arrangement, the bolts 19 are circumferentially provided by a number of 12 at positions having a diameter of 220 mm.
A through hole 14 for introduction of helium gas is formed in the wafer stage 40 at the center of the latter, and is covered with a ceramic susceptor 43 so as to protect the outer periphery thereof. Further, concentric temperature adjusting grooves 15 are formed in the wafer stage 40, and are communicated with an introduction port 44 and a discharge port 45 which are formed piercing through the flange 5 and the insulation member, and through which the temperature adjusting grooves 15 are connected to pipe lines 46, 47.
Each of these pipe lines 46, 47 has a double pipe structure in order to prevent occurrence of dew formation even though coolant having a low temperature such as xe2x88x9240 deg.C. is circulated therethrough, and internal pipe lines 48, 49 are vacuum-insulated from heat. It is noted here that the above-mentioned introduction port 44 and the discharge port 45 are provided at positions having a distance of 100 mm from the center.
The pusher pins 50 serve to peel off the wafer 1 attracted to the wafer stage 40, and accordingly, it is configured to move up and down in association with telescopic motion of a transfer mechanism which is not shown and bellows 51. The number of the pusher pins 50 is three which are located at positions with a radius of 50 mm.
Next, the wafer stage 40 is connected to a high frequency power source 20 in a condition in which it is electrically isolated from the flange 50 by means of an insulating connection part 18, and accordingly, it can be applied with a bias voltage having a frequency of, for example, 800 kHz. Thus, a bias potential is effected at the wafer 1 so as to effectively introduce ions in order to carry out anisotropic etching or increase the etching rate, thereby it is possible to enhance the etching performance.
However, since the injection of the ions causes heat generation, should the ions are injected to the wafer, the wafer would be heated up to a high temperature. Accordingly, as mentioned above, coolant having a temperature which has been adjusted to a predetermined temperature is circulated through the temperature adjusting grooves 15 formed in the wafer stage 40, from an external temperature adjusting machine.
However, even with a normal etching condition, the pressure of a processing chamber or the vacuum chamber 9 is low, that is, not higher than several Pa. Accordingly, the thermal resistance between the wafer 1 and the wafer stage 40 is high so that no sufficient cooling effect can be obtained. Thus, inert gas having a relatively high thermal conductivity, such as helium gas, is introduced between the wafer 1 and the wafer stage 40 by way of the through holes 14 in order to aim at improving the thermal conductivity. It is noted that the pressure of this gas is adjusted by controlling a flow rate controller 25 in accordance with a value detected by a pressure gauge 24 connected to a pipe line 23.
It is noted that D.C. current is applied to the wafer stage 40 from a D.C. power source 22 so as to electrostatically attract the wafer 1 in order to prevent the wafer from coming off from the wafer stage 40 by a pressure of the gas which is set to a value in a rage of about 500 to 3 k Pa. That is, since the wafer 1 makes contact with the plasma, it is held at a potential which is substantially the same as that of the vacuum chamber 9, and accordingly, a potential difference is caused between the wafer 1 and the wafer stage 40 so that the wafer 1 is electrostatically attracted by a Coulomb""s force by a charge effected in a dielectric film 21.
Next, explanation will be made of a prior art technology 10 shown in FIG. 10. In this case, the configuration including, for example, the upper electrode is the same as that of the prior art technology shown in FIG. 9, but the diameter of the wafer stage 40 is enlarged to 340 mm in order to cope with a wafer 95 having a diameter of 12 inches. Accordingly, the sizes of the insulation member 7 and the flange 5 for securing the wafer stage 40 are changed.
Specifically, the convex part (upper part) of the wafer stage on which the wafer 95 is set, has a diameter of 90 mm, screws 19 with which the wafer stage is secured to the insulation member 7 are located at positions with a diameter of 320 mm. Further, since the distribution of heat input to a wafer on processing is different between a wafer having 8 inches and a wafer having 12 inches, it is required to change the configuration of the temperature adjusting grooves 15, and as a result, the introduction port 44 and the discharge port 45 connecting the temperature grooves 15 and the pipe lines are shifted to positions having a distance of 145 mm from the center. Thus, the dimensions and the structure thereof are completely different from those of the processing apparatus for 8 inch wafers.
Thus, in the prior art technology, the dimensions and the structure of the apparatus are different among sizes of wafers and accordingly, the above-mentioned problems are caused. In detail, in the consideration of the stand point of an apparatus manufacturer, a problem of heavy burden upon the designers is caused. That is, new design is required for all component parts for every one of different wafer sizes. However, almost semiconductor manufacturing apparatus have complicated structures with a large number of component parts, and accordingly, the labor costs for the designers are increased. As a result, the apparatus becomes expensive.
As to a next problem, a large number of component parts should be managed, and accordingly, stock components reserved in a firm is increased. Further, due to the large number of component parts, a disposal which should be taken for a trouble raised on the client side is delayed, which becomes a secondary problem. Further, in this case, the delivery of component parts to the client side is finally made by worker, but since almost cases are such that not only a larger number of component parts are present but also component parts have shapes which are similar to one another except their dimensions, it is likely to cause errors during the delivery.
Next, as to a hindrance caused on the user side, first of all, the introduction cost of the apparatus is expensive. That is, even though a processing apparatus for wafers having a certain size is owned, since the structure of the lower part of the apparatus should be modified in its entity in order to cope with wafers having a different diameter, the apparatus cannot be immediately used. Accordingly, a new apparatus has to be introduced or the change of the diameter of wafers should be given up.
Further, the above-mentioned problem is not always limited to the enlargement of the size of wafer. For example, even though a processing apparatus capable of processing wafers having a 12 inch diameter has been introduced, there might be often caused such a case as to process wafers having a 8 inch diameter. In this case, although a wafer having a 8 inch diameter may be set on a wafer stage for a wafer having a 12 inch diameter, this wafer cannot actually be processed due to problems of a temperature distribution over the wafer and transfer of the wafer. Further, as to another problem, as already detailed in the problem of the manufacturer side, the time for replacement of component parts becomes longer.
Next, explanation will be made of hindrance caused by a wafer stage manufacture. In a relatively large number of cases, component parts relating to the wafer stage is purchased from an external supplier, and accordingly, in this case, the external wafer stage manufacturer has to change the dimensions of every component part for every of the wafer sizes, and accordingly, redesigning thereof is required. The burden upon the designers must be heavy and be increased. Further, since the specification of the wafer stage is different among apparatuses, there is a problem of increasing the kinds of stock components.
A first object of the present invention is to provide a wafer processing apparatus in which a wafer stage can be replaced with any of a plurality of inexpensive wafer stages having different functions, and a second object of the present invention is to provide an inexpensive wafer processing apparatus which can optimize the temperature distribution over the surface of the wafer.
Further, a third object of the present invention is to provide a common single wafer stage which is inexpensive and which can be used solely, instead of a plurality of wafer stages having different functions, and a fourth object of the present invention is to provide a wafer stage which is inexpensive and which can optimize the temperature distribution over the surface of a wafer.
Further, a fifth object of the present invention is to provide a wafer processing method which can maximize the processing capacity of a wafer processing apparatus.
The above-mentioned first object can be attained by a wafer processing apparatus of a type which comprises a wafer stage and processes a semiconductor wafer set on this wafer stage, wherein a wafer holding mechanism is commonly used among a plurality of wafer stages, and the aforementioned wafer stage can be changed into one of the plurality of stages having different functions in order to process the semiconductor wafer.
The first object can also attained by having a wafer stage incorporated in a wafer processing apparatus, for holding a semiconductor wafer, which can be separated from a structure to which the wafer stage is secured, and by commonly using, among a plurality of wafer stages having different functions, the positions and the structures of means for securing a wafer stage to the above-mentioned structure, component parts with which alignments between the structure and the wafer stage are required, such as for example, an electrical connection structure or a transfer mechanism for the semiconductor wafer, a cooling structure for the wafer stage, through-holes for introducing cooling gas between the semiconductor wafer and the wafer stage, or various wafer monitoring mechanisms, in order to simply change the wafer stage into the one having a different function.
Next, the second object can be attained by the provision of a heat insulating layer having a heat conductivity which is lower than that of a material of the wafer stage, in a wafer stage incorporated in a wafer processing apparatus.
Further, the third object can be attained by having a wafer stage incorporated in a wafer processing apparatus, for holding a semiconductor wafer, which can be separated from a structure to which the wafer stage is secured, by commonly using, among a plurality of wafer stages having different functions, the positions and structures of means for securing a wafer stage, components parts with which alignment is required between the structure and the wafer stage, such as an electrical connection structure or a transfer mechanism for the semiconductor wafer, a cooling structure for the wafer stage or through holes for introducing cooling gas between the semiconductor wafer and the wafer stage or various monitor mechanism for the wafer, in order to enable any of the plurality of water stages to be mounted to the structure.
Further, the fourth object can be attained by the provision of a heat insulating layer having a heat conductivity which is lower than a material of the wafer stage in the wafer stage incorporated in a wafer processing apparatus.
Further, the fifth object can be attained by monitoring a temperature of a semiconductor wafer on processing, a temperature of coolant flowing through a wafer stage or thermal data from a wafer stage, and controlling the status of the apparatus in accordance with the thermal data.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.